Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its stored data for some extended period without the application of power. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and removable memory modules, and the uses for non-volatile memory continue to expand.
Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data state of each cell. Data can be read from the memory cells by performing a read operation. Memory cells are typically programmed using erase and programming cycles. For example, memory cells of a particular block of memory cells are first erased and then selectively programmed.
These program/erase cycles cause wear of the memory cells to occur. As the memory cells wear, issues such as oxide degradation, slower performance and increased probability of failures might occur. The number of program/erase cycles can also affect data retention characteristics of the memory cells. For example, a typical memory cell might exhibit a data retention life of 20 years or a particular level of reliability for 100,000 program/erase cycles. However, the expected data retention of the memory cells is reduced as the number of program/erase cycles performed on the memory cells increases. The application where the memory device is used will typically dictate whether data retention or a high number of program/erase cycles is more important to the user. Various data management methods are utilized to address these wear issues. Methods typically referred to as wear leveling methods (e.g., operations) are performed on memory cells in order to address these wear issues in memory devices. Generally, wear leveling refers to moving data and/or adjusting where data is stored in the memory device in an attempt to spread the wear effects around the device.
One type of wear leveling operation is dynamic wear leveling and is typically managed by a host system (e.g., processor) utilizing the memory device. The host system monitors memory usage in the device to determine if particular memory locations are experiencing more program/erase cycles than other memory locations in the memory device. Thus, the host system dynamically adjusts its addressing of memory locations in the memory device to reduce the number of program/erase cycles the particular memory locations experience relative to other memory locations in the memory device.
Another type of wear leveling operation is static wear leveling which performs wear leveling operations in a uniform manner without focusing on usage of particular memory locations as is done in dynamic wear leveling. Static wear leveling operates essentially independent of how often the host system is accessing particular locations in memory, for example.
Whether dynamic or static wear leveling methods are being employed, data stored in the memory device which is not being modified (e.g., changed or updated) might still be moved from one memory location to another. This movement of data results in additional program/erase cycles which can lead to an unwanted reduction in data retention characteristics as discussed above.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present disclosure, there is a need in the art for alternate methods for managing wear leveling operations in memory devices.